1. Field of the Invention
This invention relates to active matrix array devices, and in particular to active matrix devices in which digital to analogue converter circuitry is provided for generating the drive signals for the individual device pixels. For example, the invention relates to display devices. In typical display configurations, analogue drive signals are provided to columns of the active matrix array, and the digital to analogue converter circuitry is then part of the column driver circuitry.
2. Description of the Related Art
Low temperature poly-Si (LTPS) active matrix displays normally have integrated row and source (or column) drivers to reduce interconnect complexity and cost. In the case of the column driver there is also a big incentive to integrate digital-to-analogue converters (DACs), so that the interface to the glass is digital. This reduces the overall cost of the display module and enables the display controller to be fabricated in a standard digital CMOS process flow.
The use of resistor string digital to analogue converters is known in the column driver circuitry of active matrix liquid crystal (LC) displays. A single resistor string is typically used to supply a large number of converter circuits, as this ensures good uniformity of the output voltages of the converters. The resistor string comprises a resistor or a set of resistors connected in series with connections being made at various points along the length of the string. A voltage is applied to each end of the resistor string, and in addition voltages may also be applied to intermediate points along the string. The outputs are taken from various points along the length of the string and the voltages present at these points represent the analogue output voltage levels of the digital to analogue converters. These voltages may be distributed evenly across the voltage range in order to produce a converter with a linear output voltage characteristic, or they may be arranged to produce a non-linear characteristic.
In most cases the drive voltages applied to the source (or column) lines of an active matrix display do not have a linear dependence upon digital code. This is because the source driver output voltages have to correct for the particular voltage dependence of the electro-optical effect being used in the display (e.g. liquid crystal cell or light emitting diode) and then to provide the appropriate brightness versus digital code relationship (gamma correction).
A resistor string provides a convenient way to achieve gamma correction (namely to generate the appropriate non-linear output voltage versus digital code). The resistor string generates a set of reference voltages (64 in the case of a 6 bit DAC). A decoder and voltage selector circuit is then used to decode the digital input and select 1 of the 64 reference voltages. The required nonlinearity can be achieved by changing the value of resistance between the points where outputs are taken from the resistor string and by modifying the values of the voltages applied to points within the resistor string.
This technique has been used in LTPS displays, but suffers from the disadvantage that the design rules used in poly-Si result in much larger decoders than is desirable (particularly for 6 bit DACs or greater).
It is also known that using a 2-stage resistor-capacitor hybrid DAC (T Nakamura et al Asia Display conference proceedings 2001, p 1603) results in a significantly smaller converter. This type of approach was used even earlier in crystalline Si ICs (J W Yang and K W Martin IEEE J. Solid-State Circuits, 24, p 1458 (1989)). In this type of converter, the resistor string is used to generate a number of pairs of reference voltages. The most significant bits (MSBs) are then used to select a pair of reference voltage that are used as the input to the second stage capacitive converter, the digital inputs to which are the LSBs. For example, to achieve a 6 bit conversion the 3 MSBs could be used to select 1 pair of reference voltages (Vl and Vh) from 8 pairs and the 3 LSBs are then used to generate an output voltage between Vl and Vh according to the digital data. The second stage capacitive conversion is linear between Vl and Vh and the gamma correction is provided by the 3 MSB resistor string DAC. The overall conversion can therefore be described as “piece-wise linear”.
A block diagram illustrating how such a 6-bit 2-stage DAC can be implemented using known techniques in a LTPS display is shown in FIG. 1.
The DAC 10 comprises a pair of latches 12 for latching the 6 bit pixel data to a first DAC 14 which has as input the 3 most significant bits (MSBs) of the pixel data. This 3 bit DAC 14 functions as a voltage selector, for outputting high and low voltage rails Vh and Vl. These voltage levels are selected from the reference voltages Vrefs from a resistor string 15.
The 3 least significant bits (LSBs) are used to control a 3 bit DAC 16, in the form of a switched capacitor DAC 18 (“C-DAC”) and a switched capacitor buffer amplifier 20 (“SC buffer amp”). The output is supplied to the columns of the pixel array through a 3:1 multiplexer and column pre-charge circuit 22.
FIG. 2 shows how the second stage 16 consisting of the 3 LSB capacitive DAC 18 and buffer amplifier 20 can be implemented using known techniques.
The value of the feedback capacitor in FIG. 2 is 8C, which is required to set the correct gain for the inverting amplifier. A value of 8C ensures the output voltage from the amplifier increases linearly from Vl at LSB binary code 000 to Vl+7(Vh−Vl)/8 at LSB binary code 111. Thus, the voltage increments by (Vh−Vl)/8 in 7 equal steps between code 000 and 111.
The stage 16 is operable in two modes. In a setup mode (with Ck2 high and Ck1 low), the inverting input and output of the amplifier are connected together. This means that one side of the 8C feedback capacitor (24) is charged to the built in offset voltage of the amplifier, while the other side of the feedback capacitor is charged to Vl. At the same time all the input capacitors are charged to Vh.
During an output (or active) mode (with Ck1 high and Ck2 low), the input voltages applied to the input capacitors (C, 2C and 4C) are switched from Vh to Vl if the value of the corresponding LSB data bit (B0, B1 and B2) is equal to one. If the LSB data value is equal to zero, the corresponding input voltage remains at Vh. This causes the output voltage of the inverting amplifier to increase linearly with the value LSB data, from Vl at LSB binary code 000 to Vl+7(Vh−Vl)/8 at LSB binary code 111. The resulting output voltage is given by the equation shown in FIG. 2.
The second stage DAC of FIG. 2 is well known and referred to as a charge redistribution switched capacitor converter. It is particularly well suited to LTPS technology because the switched capacitor circuit corrects for offset voltage variations in the amplifier, which are large in LTPS technology due to large variations in the electrical characteristics of the thin film transistors.
In FIG. 2, the amplifier shown is a single input high gain, inverting amplifier. However the same operation can be achieved using any conventional high open-loop gain differential input amplifier where the positive terminal is connected to a grounded potential and the capacitors and feedback are connected to the inverting input.
Although the approach shown in FIGS. 1 and 2 offers a more compact DAC than a single stage resistor string, the layout area using LTPS technology is still undesirably large. For current and future display resolutions this means that it is not possible to have a single DAC per column. Instead, the output from each DAC must be multiplexed across a number of columns. In the example shown in FIG. 1, the multiplex ratio is 3:1, which is fairly typical. The use of multiplexing allows the output of each converter circuit to be connected to one of a number of columns in the display, reducing the amount of circuitry which must be integrated on the display substrate.
In LTPS technology, minimum feature sizes are relatively large (typically several microns), which means that the digital parts (data latches and voltage selector circuits) normally consume a larger area than the LSB capacitor DAC and amplifier. Whilst increasing the multiplex ratio reduces the area of the poly-Si circuits, it also requires the buffer amplifier to be significantly faster. For example, for the case of the 3:1 mutliplex ratio illustrated in FIG. 1 the buffer must reach its settling voltage in just ⅓ of the time compared with a 1:1 ratio. This speed constraint is made worse because the switched capacitor circuit operates over 2 phases of roughly equal period and the output voltage is only valid during the active phase (ck1 high in FIG. 2) and is not valid during the set up phase (ck2 high in FIG. 2). This means for example that in the case of a 3:1 multiplexer the settling time of the amplifier must be less than ⅙ of the line time.
It is clear from the above that there is an amplifier speed versus layout area trade-off, which is a particularly acute in higher resolution displays with a small column pitch.
This invention relates in particular to the implementation of the LSB DAC and the consequences that this has on the number of digital data latches that are required on the data input side.